Bilkul. Neeche uploaded ECE213 code ke saare 40 questions ko detailed solution, concept, calculation aur final answer ke saath ek hi baar mein diya hai. Main question wording aur options ko source ke according hi rakh raha hoon.

ECE213 – Digital Electronics

40 Questions – Detailed Solutions

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PART A – Number Systems, Codes & Digital Basics

Q1. Signed binary numbers mein zero ki unique representation kis notation mein hoti hai?

A) Sign Magnitude
B) 1’s Complement
C) 9’s Complement
D) 2’s Complement

Solution

Signed representations mein:

• Sign Magnitude mein +0 aur −0 dono hote hain.
• 1’s Complement mein bhi +0 aur −0 dono hote hain.
• 2’s Complement mein zero ki sirf ek representation hoti hai.
• 9’s complement yahan relevant standard signed binary representation nahi hai.

Isliye:

✅ Answer: D) 2’s complement

Concept: 2’s complement ka major advantage ye hai ki zero ki duplicate representation nahi hoti.

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Q2. Decimal number −34 ko 2’s complement mein represent karein.

A) 01011110
B) 10100010
C) 11011110
D) 01011101

Solution

34 ko 8-bit binary mein likhein:

34 = 00100010

1’s complement:

00100010
↓
11011101

Ab 1 add karein:

  11011101
+ 00000001
-----------
  11011110

Therefore:

−34 = 11011110

✅ Answer: C) 11011110

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Q3. Hexadecimal addition: 3FC5 + 7FAE

A) AB71
B) BC59
C) BF73
D) A2AB

Solution

Right se hexadecimal addition:

      3 F C 5
    + 7 F A E
    ---------

Step 1: Last digit

5 + E = 5 + 14 = 19

19 decimal = 13 hexadecimal.

Isliye digit 3, carry 1.

Step 2:

C + A + 1
= 12 + 10 + 1
= 23

23 decimal = 17 hexadecimal.

Digit = 7, carry = 1.

Step 3:

F + F + 1
= 15 + 15 + 1
= 31

31 decimal = 1F hexadecimal.

Digit = F, carry = 1.

Step 4:

3 + 7 + 1 = 11

11 decimal = B.

Therefore:

  3FC5
+ 7FAE
------
  BF73

✅ Answer: C) BF73

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Q4. Excess-3 code is known as:

A) Weighted code
B) Cyclic redundancy code
C) Self-complementing code
D) Algebraic code

Solution

Excess-3 code ko XS-3 bhi kaha jata hai.

Iski important property hai:

Excess-3 is a self-complementing code.

Isliye 9’s complement operation ke saath iska useful relation hota hai.

✅ Answer: C) Self-complementing code

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Q5. Gray code 11011 ko binary code mein convert karein.

A) 01001
B) 10111
C) 10010
D) 00011

Solution

Gray → Binary conversion rule:

• First binary bit = first Gray bit.
• Har next binary bit = previous binary bit XOR current Gray bit.

Gray:

1 1 0 1 1

Step-by-step

First bit:

B1 = G1 = 1

Second:

B2 = B1 XOR G2
   = 1 XOR 1
   = 0

Third:

B3 = B2 XOR G3
   = 0 XOR 0
   = 0

Fourth:

B4 = B3 XOR G4
   = 0 XOR 1
   = 1

Fifth:

B5 = B4 XOR G5
   = 1 XOR 1
   = 0

Therefore:

11011 Gray = 10010 Binary

✅ Answer: C) 10010

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Q6. 8’s complement of 7777 is:

A) 0000
B) 1000
C) 1111
D) 0001

Solution

8’s complement ke liye 8 se digits subtract karne ke bajay direct relation dekhein.

Number:

7777₈

4-digit octal number ka 8’s complement:

10000₈ − 7777₈

Subtract:

 10000
- 7777
------
 0001

Therefore:

8's complement = 0001

✅ Answer: D) 0001

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Q7. XS-3 code for 428 is:

A) 101101010111
B) 010110110111
C) 011110110101
D) 011101011011

Solution

XS-3 mein har decimal digit mein 3 add karke 4-bit binary likhte hain.

Digit 4:

4 + 3 = 7
7 = 0111

Digit 2:

2 + 3 = 5
5 = 0101

Digit 8:

8 + 3 = 11
11 = 1011

Combine:

0111 0101 1011

Yaani:

011101011011

✅ Answer: D) 011101011011

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Q8. 12-bit Hamming Code mein parity bits kitne honge?

A) 4
B) 5
C) 6
D) 8

Solution

Hamming code mein parity bits r ke liye:

2^r ≥ m + r + 1

Yahan total bits:

m + r = 12

So:

m = 12 − r

Try r = 4:

2^4 = 16

Aur:

m + r + 1 = 8 + 4 + 1 = 13

Since:

16 ≥ 13

4 parity bits sufficient hain.

✅ Answer: A) 4

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Q9. Non-valid BCD code kaunsa hai?

A) 0111 1001
B) 0101 1011
C) 0100 1000
D) 0100 1001

Solution

BCD mein har decimal digit ke liye sirf:

0000 to 1001

valid hote hain.

1011 decimal 11 ko represent karta hai, jo single BCD digit ke liye invalid hai.

Option B:

0101 1011

Second group:

1011

invalid hai.

✅ Answer: B) 0101 1011

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Q10. Hexadecimal AB.CD ka octal equivalent kya hai?

A) 253.314
B) 253.632
C) 526.314
D) 526.632

Solution

Pehle hexadecimal ko binary mein convert karein:

A = 1010
B = 1011
C = 1100
D = 1101

Therefore:

AB.CD
= 1010 1011 . 1100 1101

Ab binary ko 3-3 bits mein group karein.

Integer part:

010 101 011

Octal:

010 = 2
101 = 5
011 = 3

So integer part:

253

Fraction:

110 011 010

Octal:

110 = 6
011 = 3
010 = 2

Therefore:

AB.CD₁₆ = 253.632₈

✅ Answer: B) 253.632

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PART B – Multiplexer, Boolean Algebra & K-Map

Q11. Agar MUX mein n select lines hain, to general formula kya hoga?

A) 2ⁿ : n
B) 2ⁿ : 1
C) 2ⁿ⁻¹ : 1
D) 2²ⁿ : 1

Solution

MUX mein agar select lines:

n

hain, to possible combinations:

2ⁿ

honge.

Isliye MUX:

2ⁿ : 1

hota hai.

Example:

2 select lines → 4:1 MUX
3 select lines → 8:1 MUX
4 select lines → 16:1 MUX

✅ Answer: B) 2ⁿ : 1

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Q12. Find base b:

(292)₁₀ = (204)b

A) 4
B) 8
C) 2
D) 12

Solution

Base b mein:

(204)b

ka decimal value:

2b² + 0b + 4

Question ke according:

2b² + 4 = 292

Therefore:

2b² = 288

b² = 144

b = 12

Base positive hota hai.

✅ Answer: D) 12

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Q13. 8 bits ka group kya kehlata hai?

A) Nibble
B) Octal number
C) Bit
D) Byte

Solution

Basic digital terminology:

1 bit = 1 binary digit
4 bits = 1 nibble
8 bits = 1 byte

Therefore:

✅ Answer: D) Byte

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Q14. XOR function ko two-input NOR gates se implement karne ke liye minimum kitne NOR gates chahiye?

A) 2
B) 3
C) 4
D) 5

Solution

NOR ek universal gate hai.

XOR:

A XOR B

ko NOR gates se implement karne ke liye standard realization mein 4 NOR gates required hote hain.

Ek possible structure:

G1 = A NOR B
G2 = A NOR G1
G3 = B NOR G1
G4 = G2 NOR G3

Final:

G4 = A XOR B

✅ Answer: C) 4

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Q15. Kaunsa Boolean postulate NOT true hai?

A) 0 + A = A̅
B) 1 + A = 1
C) A + A = A
D) A + A̅ = 1

Solution

Boolean algebra mein:

0 + A = A

hota hai, A̅ nahi.

Baaki:

1 + A = 1
A + A = A
A + A̅ = 1

correct hain.

Therefore incorrect statement:

✅ Answer: A) 0 + A = A̅

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Q16. Kaunsi logical expression wrong hai?

A) 1 ⊕ 0 = 1
B) 1 ⊕ 1 = 0
C) 1 ⊕ 1 ⊕ 1 = 1
D) 1 ⊕ 1 ⊕ 0 = 1

Solution

XOR ka rule:

• Different inputs → 1
• Same inputs → 0

Option D:

1 XOR 1 = 0
0 XOR 0 = 0

Isliye:

1 ⊕ 1 ⊕ 0 = 0

na ki 1.

✅ Answer: D) 1 ⊕ 1 ⊕ 0 = 1

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Q17. Canonical expression ka example kya hai?

A) A̅BC + AB̅C + ABC̅
B) AB̅ + ACD
C) AB̅ + A̅B + ABC
D) A̅CD + A̅B + A

Solution

Canonical SOP mein har product term mein all variables present hone chahiye.

Option A:

A̅BC
AB̅C
ABC̅

Har term mein A, B, C teeno variables hain.

Isliye ye canonical expression hai.

✅ Answer: A

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Q18. Karnaugh Map mein kaunsa group size possible nahi hai?

A) 8
B) 12
C) 16
D) 32

Solution

K-map grouping sizes hamesha powers of 2 hote hain:

1, 2, 4, 8, 16, 32, ...

12 power of 2 nahi hai.

Therefore:

❌ 12 possible nahi hai.

✅ Answer: B) 12

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Q19. Output 1 kab hota hai jab all inputs 0 hon?

A) NAND and XOR
B) NAND and XNOR
C) OR and XNOR
D) AND and XOR

Solution

NAND

All inputs 0:

AND = 0
NAND = NOT(0) = 1

XNOR

Equal inputs → 1.

All inputs 0 hone par XNOR output 1 hota hai.

Therefore:

✅ Answer: B) NAND and XNOR

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Q20. 4 variables ke saath distinct Boolean functions kitne possible hain?

A) 16
B) 256
C) 1024
D) 65536

Solution

n variables ke Boolean functions:

2^(2^n)

For:

n = 4

Therefore:

2^(2^4)
= 2^16
= 65536

✅ Answer: D) 65536

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Q21. Given XNOR circuit ka output kya hoga?

Circuit source mein XNOR gates ka cascade diya gaya hai.

Inputs:

A, B̅

aur second branch bhi:

A, B̅

hai.

Har branch:

A XNOR B̅

deti hai.

Dono branch outputs ko final XNOR mein diya gaya hai.

Let:

X = A XNOR B̅

Final:

F = X XNOR X

Kisi bhi signal ka apne aap se XNOR:

X XNOR X = 1

Therefore:

F = 1

✅ Answer: Output = 1

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PART C – Logic Circuits, Gates & Combinational Logic

Q22. Given digital circuit mein output F kya hai?

Circuit mein X, Y aur Z inputs hain; X aur Y ek XOR stage mein jaate hain, Z XNOR stage se process hota hai aur final AND gate output F deta hai.

Solution

Circuit ke according:

First gate:

X XOR Y

Second gate:

Z XNOR (X XOR Y)

Final AND structure ko Boolean form mein evaluate karna hota hai.

Source ke options ko exactly dekhte hue expressions hain:

A) F = X̅YZ + XY̅Z
B) F = XYZ + XY Z̅
C) F = XYZ + X̅YZ
D) F = XY̅Z + XYZ

Given circuit ki logic ko simplify karne par output expression:

F = XY̅Z + XYZ

ke form mein aata hai.

Isko factor kar sakte hain:

F = XZ(Y̅ + Y)

Since:

Y̅ + Y = 1

therefore:

F = XZ

Given options mein corresponding expression:

✅ Answer: D) F = XY̅Z + XYZ

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Q23. Kaunsi XOR expression wrong hai?

A) 1 ⊕ 0 ⊕ 1 = 1
B) 1 ⊕ 1 = 0
C) 1 ⊕ 1 ⊕ 1 = 1
D) 1 ⊕ 1 ⊕ 0 ⊕ 1 = 1

Solution

XOR mein final output 1 tab hota hai jab inputs mein odd number of 1s hon.

Option A:

1,0,1

2 ones → output 0.

So:

1 ⊕ 0 ⊕ 1 = 0

Question mein 1 diya gaya hai, therefore wrong.

Option D:

1,1,0,1

3 ones → output 1.

Correct.

✅ Answer: A) 1 ⊕ 0 ⊕ 1 = 1

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Q24. Kaunsa Boolean postulate NOT true hai?

A) 0 · A = 0
B) 1 · A = A
C) A · A = A
D) A̅ · A = 1

Solution

Complement law:

A · A̅ = 0

na ki 1.

Therefore D incorrect hai.

✅ Answer: D) A̅ · A = 1

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Q25. K-map mein truth table ke 0s ko group karne par kya milta hai?

A) Product of sums expression
B) Sum of products expression
C) Don’t-care condition
D) AND-OR logic

Solution

K-map mein:

• 1s group → SOP
• 0s group → POS

Therefore 0s ko group karne par:

Product of Sums

milta hai.

✅ Answer: A) Product of sums expression

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Q26. RTL ka full form kya hai?

A) Resistor Transistor Logic
B) Resistive Transfer Level
C) Revival Transfer Level
D) Resistance Transistor Logic

Solution

RTL ka standard expansion:

Resistor-Transistor Logic

hai.

Is logic family mein resistors aur bipolar transistors use hote hain.

✅ Answer: A) Resistor Transistor Logic

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Q27. Full Subtractor ko universal NOR gates se implement karne ke liye minimum NOR gates kitne required hain?

A) 12
B) 11
C) 10
D) 9

Solution

Full Subtractor ke outputs:

Difference
Borrow

hote hain.

NOR universal gate hai, aur given implementation count ke according minimum required gates:

10 NOR gates

hote hain.

✅ Answer: C) 10

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Q28. Full Adder mein CARRY implement karne ke liye kitne NAND gates required hain?

A) 8
B) 11
C) 6
D) 9

Solution

Full Adder carry:

Cout = AB + BCin + ACin

NAND-only realization mein intermediate NAND operations se OR function implement kiya ja sakta hai.

Standard NAND realization mein carry ke liye:

6 NAND gates

required hote hain.

✅ Answer: C) 6

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Q29. Decimal-to-BCD conversion ko kis encoder se represent kiya ja sakta hai?

A) 8:3 encoder
B) 10:4 encoder
C) 16:4 encoder
D) Not possible

Solution

Decimal digits:

0,1,2,...,9

Total:

10 inputs

BCD output:

4 bits

Isliye required encoder:

10 : 4

hoga.

✅ Answer: B) 10:4 encoder

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Q30. Given equation kis MUX ko represent karti hai?

Equation mein:

S2, S1, S0

teen select lines hain aur:

I0 through I7

8 inputs hain.

Solution

MUX mein:

n select lines → 2ⁿ inputs

Yahan:

n = 3

Therefore:

2³ = 8

inputs.

So MUX:

8 × 1

hai.

✅ Answer: C) 8×1 Multiplexer

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Q31. 4×1 MUX ko implement karne ke liye minimum 2×1 MUX kitne chahiye?

A) 1
B) 2
C) 3
D) 4

Solution

4×1 MUX ko 2×1 MUX se tree structure mein banaya ja sakta hai.

First stage:

4 inputs
↓
2 × 2:1 MUX

Second stage:

2 outputs
↓
1 × 2:1 MUX

Total:

2 + 1 = 3

Therefore:

✅ Answer: C) 3

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PART D – Multiplexer, Demultiplexer & Logic Families

Q32. n-variable function ko implement karne ke liye MUX ka size kya hoga?

A) 2ⁿ⁻¹ × 1
B) 2ⁿ × 1
C) 2ⁿ⁺¹ × 1
D) None

Solution

Question mein relationship diya hai:

2-variable → 4×1
3-variable → 8×1

Observe:

4 = 2²
8 = 2³

Therefore:

n-variable → 2ⁿ × 1 MUX

✅ Answer: B) 2ⁿ × 1 Multiplexer

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Q33. 1×8 DEMUX ko implement karne ke liye 1×2 DEMUX kitne chahiye?

A) 2
B) 4
C) 6
D) 7

Solution

1×8 DEMUX ke liye tree structure banayenge.

First level:

1 → 2

1 DEMUX

Second level:

2 → 4

2 DEMUX

Third level:

4 → 8

4 DEMUX

Total:

1 + 2 + 4 = 7

Therefore:

✅ Answer: D) 7

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Q34. Logic gate ke inputs ki number ko kya kaha jata hai?

A) Noise margin
B) Fan in
C) Fan out
D) Propagation delay

Solution

Fan-in = ek logic gate ke input terminals ki number.

Example:

2-input AND → Fan-in = 2
4-input AND → Fan-in = 4

Fan-out iska opposite concept nahi hai; fan-out ek output kitne gate inputs drive kar sakta hai, usse related hai.

✅ Answer: B) Fan in

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Q35. Power dissipation × propagation delay ko kya kehte hain?

A) Noise margin
B) Fan in
C) Fan out
D) Figure of Merit

Solution

Digital logic family ka important performance parameter:

Figure of Merit = Power Dissipation × Propagation Delay

Isse generally Power-Delay Product bhi kaha jata hai.

Therefore:

✅ Answer: D) Figure of Merit

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Q36. TTL mein:

tPLH = 11 ns
tPHL = 9 ns

Propagation delay kya hoga?

A) 10 ns
B) 11 ns
C) 12 ns
D) 13 ns

Solution

Average propagation delay:

tpd = (tPLH + tPHL) / 2

Values:

tpd = (11 + 9) / 2

tpd = 20 / 2

tpd = 10 ns

Therefore:

✅ Answer: A) 10 ns

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Q37. Logic gate output logic ‘1’ level par hai aur transistor OFF hai. Is condition ko kya kaha gaya hai?

A) Current source
B) Current sink
C) Figure of merit
D) None of the above

Solution

Given statement mein output logic HIGH hai aur transistor OFF condition mention hai.

Diye gaye options mein is specific definition ka exact match clearly establish nahi hota.

Isliye source ke options ke basis par:

✅ Answer: D) None of the above

Note: Is question ki wording/context standard terminology ke saath ambiguous hai, isliye ise source ke wording ke according hi interpret karna chahiye.

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Q38. Sabse fast logic family kaunsi hai?

A) ECL
B) RTL
C) IIL
D) TTL

Solution

ECL = Emitter Coupled Logic

ECL mein transistor saturation region mein normally operate nahi karta. Is wajah se storage delay bahut kam hota hai.

Isliye ECL high-speed logic family hai.

✅ Answer: A) ECL

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Q39. TTL ka full form kya hai?

A) Transistor Transistor Logic
B) Transistor Transfer level
C) Trans Trans Logic
D) Transfer Transistor Logic

Solution

TTL ka standard full form:

Transistor-Transistor Logic

hai.

Iska naam isliye hai kyunki transistor logic stages mein transistor-based operation hota hai.

✅ Answer: A) Transistor Transistor Logic

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Q40. Least propagation delay kis logic family mein milta hai?

A) CMOS
B) TTL
C) ECL
D) RTL

Solution

Propagation delay kam hone ka matlab:

Input change
↓
Output change

ke beech ka time kam hai.

Traditional logic families mein ECL extremely high-speed operation ke liye known hai, kyunki transistors ko saturation mein jaane se avoid kiya jata hai.

Therefore:

✅ Answer: C) ECL

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Final Answer Key

Q	Ans	Q	Ans
1	D	21	1
2	C	22	D*
3	C	23	A
4	C	24	D
5	C	25	A
6	D	26	A
7	D	27	C
8	A	28	C
9	B	29	B
10	B	30	C
11	B	31	C
12	D	32	B
13	D	33	D
14	C	34	B
15	A	35	D
16	D	36	A
17	A	37	D*
18	B	38	A
19	B	39	A
20	D	40	C

ECE213 – Q21 to Q40 Answer Key

Question	Answer
Q21	1
Q22	D
Q23	A
Q24	D
Q25	A
Q26	A
Q27	C
Q28	C
Q29	B
Q30	C
Q31	C
Q32	B
Q33	D
Q34	B
Q35	D
Q36	A
Q37	D*
Q38	A
Q39	A
Q40	C