COURSE CODE: ECE213

COURSE NAME: DIGITAL ELECTRONICS

Time Allowed: 03:00 hrs
Max. Marks: 70

Instructions

Read the following instructions carefully before attempting the question paper.
This question paper is divided into two parts A and B.
Attempt all the questions in serial order.
Part A contains 20 questions of 1 mark each. 0.25 marks will be deducted for each wrong answer.
Part B contains 5 questions of 10 marks each. In each question attempt either question (a) or (b), in case both (a) and (b) questions are attempted for any question only the first attempted question will be evaluated.
Do not write anything on the question paper except your registration number at the designated space.
Match the Paper Code shaded on the OMR sheet with the Paper Code mentioned on the question paper and ensure that both are the same.
After completion of first 45 minutes, the OMR sheet will be taken by the invigilator.
Submit the question paper and the rough sheet(s) along with the answer sheet to the invigilator before leaving the examination hall.

PART A

Multiple Choice Questions

Q1. Which of the following is not the type of a flip flop?

A) JK
B) T
C) RS
D) ST

Q2. Master-slave flip-flop consists of:

A) 2 flip-flops
B) 3 flip-flops
C) 4 flip-flops
D) 5 flip-flops

Q3. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz square wave as clock input. The Q output is:

A) Constant LOW
B) Constant HIGH
C) 20 kHz square wave
D) 10 kHz square wave

Q4. The symbols on this flip-flop device indicate:

             ┌─────────┐
D ──────────►│         │─── Q
             │         │
CLK ─────○▷──│         │─── Q̅
             └─────────┘

A) Triggering takes place on the negative-going edge of the CLK pulse.

B) Triggering takes place on the positive-going edge of the CLK pulse.

C) Triggering can take place anytime during the HIGH level of the CLK waveform.

D) Triggering can take place anytime during the LOW level of the CLK waveform.

Q5. In the characteristic table of D flip-flop the next state is equal to:

A) Present state
B) Set state
C) Reset state
D) D state

Q6. In SR flip-flop with S = 0 and R = 1, next state will be:

A) Same as previous state
B) Reset state
C) Set state
D) Complement of previous state

Q7. MOD-8 Counter counts up to:

A) 3
B) 6
C) 7
D) 8

Q8. CLB is the acronym for:

A) Configurable Logic Block
B) Configurable Logic Buffer
C) Critical Logic Buffer
D) Constant Logic Buffer

Q9. The code letters A through F are used for decimal equivalent values from:

A) 1 through 6
B) 9 through 14
C) 10 through 15
D) 11 through 17

Q10. An informational signal that makes use of binary digits is considered to be:

A) Solid state
B) Digital
C) Analog
D) Non-oscillating

Q11. The characteristic equation of J-K flip-flop is:

A) J’Q + KQn

B) JQ̅n + K’Qn

C) JQn + K’Qn

D) JQn + KQn

Q12. How many flip-flop circuits are needed to design a counter divided by 16?

A) One
B) Two
C) Eight
D) Sixteen

Q13. With a JK master-slave flip-flop the master is clocked when the clock is:

A) High
B) Low
C) Either low or high
D) Constant

Q14. Which of the following PLDs can be used for implementing basic logic functions?

A) PLA
B) CPLD
C) PAL
D) SLD

Q15. PAL has a:

A) Programmable AND plane only
B) Programmable OR plane only
C) Both Programmable AND and OR plane
D) None of these

Q16. Which of the following is true for PAL?

A) Once programmed, it can be reprogrammed.
B) Once programmed it cannot be reprogrammed.
C) Once programmed, it generated HIGH at the outputs.
D) Once programmed, it generates LOW at the outputs.

Q17. Programmable Logic Devices (PLDs) is a structure of:

i) Thousands of basic logic gates
ii) Advanced sequential logic functions

A) Only i)
B) Only ii)
C) Both i) and ii)
D) None

Q18. What is RAM?

A) Readily Available Memory
B) Read Only Memory
C) Random Access Memory
D) Resettable Automatic Memory

Q19. What is the storage element used in Static RAM?

A) Resistor
B) Capacitor
C) Flip Flop
D) Diode

Q20. A 64-bit word consists of how many bytes?

A) 2
B) 4
C) 8
D) 10

PART B

Descriptive / Long Answer Questions

Attempt either (a) or (b) of each question.

Q21.

a)

Implement 2-bit comparator using logic gates.

b)

i) Minimize the following function using K-map and prepare the logic circuit of end expression.

Y = Σm (1, 2, 9, 10, 11, 14, 15)

ii) Simplify the following expression using don’t care condition:

Y = Σm (1, 4, 8, 12, 13, 15) + d (3, 14)

Q22.

a)

Design a half adder and full adder using various multiplexers, give the block diagrams and explanation for each design.

b)

Design a half subtractor and full subtractor using various multiplexers, give the block diagrams and explanation for each design.

Q23.

a)

Convert SR flip-flop to JK flip-flop.

b)

Discuss in detail Master-Slave flip-flop with proper circuit diagram and characteristic table.

Q24.

a)

Detect sequence 101 using Moore machine. Draw the state diagram, state table and logic circuit.

b)

Detect sequence 111 using Mealy machine. Draw the state diagram, state table and logic circuit.

Q25.

a)

Discuss in brief the different types of semiconductor memories.

b)

What is a Programmable Logic Device (PLD)? Explain its types.

END OF QUESTION PAPER

Course Code: ECE213
Course Name: Digital Electronics
Time: 03 Hours
Maximum Marks: 70
Part A: 20 MCQs
Part B: 5 Descriptive Questions — Attempt either (a) or (b) in each question

ECE213 – DIGITAL ELECTRONICS

COMPLETE SOLUTIONS – ENGLISH

Part A + Part B

Below are the complete exam-style solutions of Q1 to Q25 in English. For questions having OR, both alternatives are solved.

ece 213 lpu solved Digital Electronics End Term Exam Question Paper

PART A – MCQ SOLUTIONS

Q1. Which of the following is not the type of a flip-flop?

A) JK
B) T
C) RS
D) ST

Answer: D) ST

Explanation:

The commonly used basic flip-flops are:

SR/RS flip-flop
JK flip-flop
D flip-flop
T flip-flop

ST flip-flop is not a standard basic flip-flop type.

Therefore:

Correct Answer: D) ST

Q2. Master-slave flip-flop consists of:

A) 2 flip-flops
B) 3 flip-flops
C) 4 flip-flops
D) 5 flip-flops

Answer: A) 2 flip-flops

Explanation:

A master-slave flip-flop consists of two stages:

Master flip-flop
Slave flip-flop

The master and slave operate during opposite phases of the clock.

Therefore:

Correct Answer: A) 2 flip-flops

Q3. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz square wave as clock input. The Q output is:

A) Constant LOW
B) Constant HIGH
C) 20 kHz square wave
D) 10 kHz square wave

Answer: D) 10 kHz square wave

Explanation:

For a JK flip-flop:

J = 1 and K = 1 → Toggle condition

The output changes its state at every active clock edge:

0 → 1 → 0 → 1 → 0 ...

Therefore, the output frequency is half of the clock frequency.

Given:

Clock frequency = 20 kHz

Therefore:

Output frequency = 20/2 = 10 kHz

Hence:

Correct Answer: D) 10 kHz square wave

Q4. The symbols on this flip-flop device indicate:

             ┌─────────┐
D ──────────►│         │── Q
             │         │
CLK ─────○▷──│         │── Q̅
             └─────────┘

A) Triggering takes place on the negative-going edge of the CLK pulse.

B) Triggering takes place on the positive-going edge of the CLK pulse.

C) Triggering can take place anytime during the HIGH level of the CLK waveform.

D) Triggering can take place anytime during the LOW level of the CLK waveform.

Answer: A) Triggering takes place on the negative-going edge of the CLK pulse.

Explanation:

The triangle at the clock input represents edge triggering.

The bubble at the clock input indicates inversion.

Therefore, the flip-flop is triggered at the:

negative-going/falling edge

of the clock.

Negative-going edge means:

1 → 0

Hence:

Correct Answer: A

Q5. In the characteristic table of D flip-flop, the next state is equal to:

A) Present state
B) Set state
C) Reset state
D) D state

Answer: D) D state

Explanation:

The characteristic equation of a D flip-flop is:

Q(next) = D

Therefore:

If D = 0:

Q(next) = 0

If D = 1:

Q(next) = 1

Hence:

Correct Answer: D) D state

Q6. In SR flip-flop with S = 0 and R = 1, next state will be:

A) Same as previous state
B) Reset state
C) Set state
D) Complement of previous state

Answer: B) Reset state

Explanation:

The characteristic table of an active-high SR flip-flop is:

S	R	Next State
0	0	No change
0	1	Reset
1	0	Set
1	1	Invalid

Given:

S = 0, R = 1

Therefore:

Q(next) = 0

This is the reset condition.

Correct Answer: B) Reset state

Q7. MOD-8 counter counts up to:

A) 3
B) 6
C) 7
D) 8

Answer: C) 7

Explanation:

A MOD-N counter has N different states.

For MOD-8:

0 → 1 → 2 → 3 → 4 → 5 → 6 → 7 → 0

Therefore, the highest count is:

8 – 1 = 7

Hence:

Correct Answer: C) 7

Q8. CLB is the acronym for:

A) Configurable Logic Block
B) Configurable Logic Buffer
C) Critical Logic Buffer
D) Constant Logic Buffer

Answer: A) Configurable Logic Block

Explanation:

CLB stands for:

Configurable Logic Block

CLBs are important building blocks in FPGA devices and contain programmable logic resources.

Correct Answer: A) Configurable Logic Block

Q9. The code letters A through F are used for decimal equivalent values from:

A) 1 through 6
B) 9 through 14
C) 10 through 15
D) 11 through 17

Answer: C) 10 through 15

Explanation:

In hexadecimal notation:

Hexadecimal	Decimal
A	10
B	11
C	12
D	13
E	14
F	15

Therefore:

A through F = 10 through 15

Correct Answer: C

Q10. An informational signal that makes use of binary digits is considered to be:

A) Solid state
B) Digital
C) Analog
D) Non-oscillating

Answer: B) Digital

Explanation:

A digital signal represents information using discrete values.

A binary digital system uses:

0 and 1

Therefore, a signal based on binary digits is called a digital signal.

Correct Answer: B) Digital

Q11. The characteristic equation of JK flip-flop is:

Answer:

Q(next) = JQ’ + K’Q

Explanation:

The JK flip-flop characteristic table is:

J	K	Q(next)	Operation
0	0	Q	No change
0	1	0	Reset
1	0	1	Set
1	1	Q’	Toggle

Therefore, the characteristic equation is:

Q(next) = JQ’ + K’Q

Correct Answer: The option containing JQ’ + K’Q

Q12. How many flip-flop circuits are needed to design a counter divided by 16?

A) One
B) Two
C) Eight
D) Sixteen

Answer: 4 flip-flops

Explanation:

For n flip-flops, the number of possible states is:

2^n

For a divide-by-16 counter:

2^n = 16

Since:

2^4 = 16

Therefore:

n = 4

Hence, 4 flip-flops are required.

Important:

The image’s printed options appear inconsistent/unclear. The correct theoretical answer is:

4 flip-flops

Q13. With a JK master-slave flip-flop, the master is clocked when the clock is:

A) High
B) Low
C) Either low or high
D) Constant

Answer: A) High

Explanation:

In the standard master-slave configuration:

Clock HIGH → Master is active
Clock LOW → Slave is active

The master captures the input during the HIGH phase and the slave transfers the information during the LOW phase.

Therefore:

Correct Answer: A) High

Q14. Which of the following PLDs can be used for implementing basic logic functions?

A) PLA
B) CPLD
C) PAL
D) SLD

Answer: A) PLA

Explanation:

PLA stands for:

Programmable Logic Array

It can implement Boolean logic functions using programmable logic arrays.

A PLA has:

Programmable AND plane
Programmable OR plane

Therefore:

Correct Answer: A) PLA

Q15. PAL has a:

A) Programmable AND plane only
B) Programmable OR plane only
C) Both Programmable AND and OR plane
D) None of these

Answer: A) Programmable AND plane only

Explanation:

PAL stands for:

Programmable Array Logic

In PAL:

AND plane = Programmable
OR plane = Fixed

In PLA:

AND plane = Programmable
OR plane = Programmable

Therefore:

Correct Answer: A) Programmable AND plane only

Q16. Which of the following is true for PAL?

A) Once programmed, it can be reprogrammed.
B) Once programmed, it cannot be reprogrammed.
C) Once programmed, it generates HIGH at the outputs.
D) Once programmed, it generates LOW at the outputs.

Answer: B) Once programmed, it cannot be reprogrammed.

Explanation:

Traditional PAL devices use fuse-based programming technology.

Once programmed, the fuse connections are permanently changed.

Therefore, traditional PAL devices are generally:

One-Time Programmable (OTP)

Hence:

Correct Answer: B

Q17. Programmable Logic Devices (PLDs) is a structure of:

i) Thousands of basic logic gates
ii) Advanced sequential logic functions

A) Only i
B) Only ii
C) Both i and ii
D) None

Answer: C) Both i and ii

Explanation:

Programmable logic devices can be used to implement many types of digital circuits, including:

Combinational logic
Sequential logic
Counters
Registers
State machines
Logic functions

Therefore, both types of logic functionality can be implemented using programmable logic devices.

Correct Answer: C) Both i and ii

Q18. What is RAM?

A) Readily Available Memory
B) Read Only Memory
C) Random Access Memory
D) Resettable Automatic Memory

Answer: C) Random Access Memory

Explanation:

RAM stands for:

Random Access Memory

In RAM, any memory location can be accessed directly.

RAM is generally volatile, meaning its stored information is lost when power is removed.

Correct Answer: C) Random Access Memory

Q19. What is the storage element used in Static RAM?

A) Resistor
B) Capacitor
C) Flip-flop
D) Diode

Answer: C) Flip-flop

Explanation:

Static RAM stores information using a bistable storage circuit/latch, commonly described as a flip-flop type storage cell.

In contrast, DRAM uses a capacitor-based storage mechanism.

Therefore:

SRAM → Flip-flop/latch based

DRAM → Capacitor based

Correct Answer: C) Flip-flop

Q20. A 64-bit word consists of how many bytes?

A) 2
B) 4
C) 8
D) 10

Answer: C) 8 bytes

Explanation:

We know:

1 byte = 8 bits

Therefore:

64 bits / 8 = 8 bytes

Hence:

64-bit word = 8 bytes

Correct Answer: C) 8

PART B – DETAILED SOLUTIONS

Q21(a). Implement a 2-bit Comparator Using Logic Gates

Let the two 2-bit numbers be:

A = A1 A0

B = B1 B0

The comparator has three outputs:

A > B
A = B
A < B

1. Equality condition

The two numbers are equal when corresponding bits are equal.

Use XNOR gates.

For MSB:

X1 = A1 XNOR B1

For LSB:

X0 = A0 XNOR B0

Therefore:

A = B = X1 X0

A = B = (A1 XNOR B1)(A0 XNOR B0)

2. A > B

A is greater than B when:

Condition 1:

A1 = 1 and B1 = 0

Condition 2:

A1 = B1 and A0 = 1 and B0 = 0

Therefore:

A > B = A1B1′ + X1A0B0′

where:

X1 = A1 XNOR B1

3. A < B

Similarly:

A < B = A1’B1 + X1A0’B0

Basic Logic Diagram

A1 ─────┐
        │
       XNOR ─── X1 ───────┐
        │                 │
B1 ─────┘                 │
                          │
A0 ─────┐                 AND ─── A = B
        │                 │
       XNOR ─── X0 ──────┘
        │
B0 ─────┘

Additional AND and OR gates are used to generate:

A > B
A = B
A < B

Q21(b)(i). Minimize the Following Function Using K-map

Given:

Y = Σm(1, 2, 9, 10, 11, 14, 15)

Assume four variables:

A, B, C, D

Minterm Table

Minterm	A	B	C	D
1	0	0	0	1
2	0	0	1	0
9	1	0	0	1
10	1	0	1	0
11	1	0	1	1
14	1	1	1	0
15	1	1	1	1

After K-map grouping, the minimized expression is:

Y = AC + B’CD’ + B’C’D

Therefore:

Final Answer:

Y = AC + B’CD’ + B’C’D

Q21(b)(ii). Simplify Using Don’t-Care Conditions

Given:

Y = Σm(1, 4, 8, 12, 13, 15) + d(3, 14)

The don’t-care terms are:

d(3,14)

In K-map minimization, don’t-care cells can be treated as either 0 or 1 depending on which choice produces larger groups and a simpler expression.

After grouping the 1s and suitable don’t-care cells:

Y = AB + AC’D’ + BC’D’ + A’B’D

Therefore:

Final minimized expression:

Y = AB + AC’D’ + BC’D’ + A’B’D

Q22(a). Design a Half Adder Using Multiplexer

A half adder adds two binary inputs.

Inputs:

A, B

Outputs:

Sum, Carry

Truth Table

A	B	Sum	Carry
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

Therefore:

Sum = A XOR B

Carry = AB

Using 4:1 MUX

Take:

S1 = A

S0 = B

Sum

AB	Sum
00	0
01	1
10	1
11	0

Therefore:

I0 = 0
I1 = 1
I2 = 1
I3 = 0

The MUX output gives:

Sum = A XOR B

Carry

AB	Carry
00	0
01	0
10	0
11	1

Therefore:

I0 = 0
I1 = 0
I2 = 0
I3 = 1

The MUX output gives:

Carry = AB

Full Adder Using MUX

A full adder has three inputs:

A, B, Cin

and two outputs:

Sum and Cout

Full Adder Equations

Sum = A XOR B XOR Cin

Cout = AB + ACin + BCin

Truth Table

A	B	Cin	Sum	Cout
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

Using an 8:1 MUX:

Select lines:

S2 = A

S1 = B

S0 = Cin

Sum inputs:

I0 = 0
I1 = 1
I2 = 1
I3 = 0
I4 = 1
I5 = 0
I6 = 0
I7 = 1

Carry inputs:

I0 = 0
I1 = 0
I2 = 0
I3 = 1
I4 = 0
I5 = 1
I6 = 1
I7 = 1

Q22(b). Design a Half Subtractor Using MUX

A half subtractor performs:

A – B

Inputs:

A = Minuend
B = Subtrahend

Outputs:

Difference
Borrow

Truth Table

A	B	Difference	Borrow
0	0	0	0
0	1	1	1
1	0	1	0
1	1	0	0

Therefore:

Difference = A XOR B

Borrow = A’B

Using 4:1 MUX

For Difference:

I0 = 0
I1 = 1
I2 = 1
I3 = 0

For Borrow:

I0 = 0
I1 = 1
I2 = 0
I3 = 0

Thus the MUX outputs implement the half subtractor.

Full Subtractor Using MUX

A full subtractor has three inputs:

A, B, Bin

Outputs:

Difference and Borrow-out

Equations

Difference = A XOR B XOR Bin

Bout = A’B + A’Bin + BBin

Truth Table

A	B	Bin	Difference	Bout
0	0	0	0	0
0	0	1	1	1
0	1	0	1	1
0	1	1	0	1
1	0	0	1	0
1	0	1	0	0
1	1	0	0	0
1	1	1	1	1

Using an 8:1 MUX:

Difference:

I0 = 0
I1 = 1
I2 = 1
I3 = 0
I4 = 1
I5 = 0
I6 = 0
I7 = 1

Borrow:

I0 = 0
I1 = 1
I2 = 1
I3 = 1
I4 = 0
I5 = 0
I6 = 0
I7 = 1

Q23(a). Convert SR Flip-Flop to JK Flip-Flop

The SR flip-flop has:

S	R	Operation
0	0	No change
0	1	Reset
1	0	Set
1	1	Invalid

The JK flip-flop has:

J	K	Operation
0	0	No change
0	1	Reset
1	0	Set
1	1	Toggle

To convert SR to JK, feedback is used.

The required inputs are:

S = JQ’

R = KQ

Verification

Case 1: J = 0, K = 0

S = 0
R = 0

Therefore:

No change

Case 2: J = 0, K = 1

S = 0
R = Q

The flip-flop performs reset operation.

Case 3: J = 1, K = 0

S = Q’
R = 0

The flip-flop performs set operation.

Case 4: J = 1, K = 1

Feedback produces the toggle operation.

Thus the SR flip-flop behaves as a JK flip-flop.

Conversion equations:

S = JQ’

R = KQ

Q23(b). Discuss Master-Slave Flip-Flop

A master-slave flip-flop consists of two flip-flops connected in cascade:

Master
Slave

The two stages operate on opposite phases of the clock.

Block Diagram

          ┌──────────┐
J ───────►│          │
K ───────►│  MASTER  │──────► SLAVE ─────► Q
          │          │
CLK ─────►│          │
          └──────────┘
                │
                ▼
             Slave
             Clock

Working

During HIGH clock

The master is enabled and captures the input information.

The slave remains disabled.

During LOW clock

The master becomes disabled.

The slave becomes enabled and transfers the master’s stored information to the output.

This arrangement prevents the output from changing repeatedly during the same clock pulse and helps avoid the race-around problem in JK flip-flops.

Characteristic Table

J	K	Q(next)	Operation
0	0	Q	No change
0	1	0	Reset
1	0	1	Set
1	1	Q’	Toggle

Characteristic Equation

Q(next) = JQ’ + K’Q

Q24(a). Detect Sequence 101 Using Moore Machine

A Moore machine produces output based only on the present state.

Required sequence:

101

Define four states:

S0 = No matching bit
S1 = First 1 detected
S2 = 10 detected
S3 = 101 detected

State Transitions

State S0

Input 0:

S0 → S0

Input 1:

S0 → S1

State S1

Input 0:

S1 → S2

Input 1:

S1 → S1

State S2

Input 0:

S2 → S0

Input 1:

S2 → S3

State S3

Sequence 101 has been detected.

Output:

For overlapping detection:

Input 0 → S0
Input 1 → S1

State Table

Present State	Input	Next State	Output
S0	0	S0	0
S0	1	S1	0
S1	0	S2	0
S1	1	S1	0
S2	0	S0	0
S2	1	S3	0
S3	0	S0	1
S3	1	S1	1

The output becomes 1 when the machine reaches S3.

Logic Circuit Procedure

To implement the Moore machine:

Encode the states using flip-flops.
Derive next-state equations from the state table.
Implement the equations using logic gates.
Connect the state output to the detection output.

Q24(b). Detect Sequence 111 Using Mealy Machine

A Mealy machine’s output depends on:

Present State + Input

Required sequence:

111

States:

S0 = No 1 detected
S1 = One consecutive 1 detected
S2 = Two consecutive 1s detected

State Transitions

S0

Input 0:

S0 → S0 / 0

Input 1:

S0 → S1 / 0

S1

Input 0:

S1 → S0 / 0

Input 1:

S1 → S2 / 0

S2

Input 0:

S2 → S0 / 0

Input 1:

S2 → S2 / 1

The third consecutive 1 produces output 1.

State Table

Present State	Input	Next State	Output
S0	0	S0	0
S0	1	S1	0
S1	0	S0	0
S1	1	S2	0
S2	0	S0	0
S2	1	S2	1

Important Difference

Moore Machine:

Output depends only on present state.

Output = f(Present State)

Mealy Machine:

Output depends on present state and input.

Output = f(Present State, Input)

Q25(a). Discuss Different Types of Semiconductor Memories

Semiconductor memory is a memory device implemented using semiconductor integrated circuits.

The two major categories are:

1. RAM

RAM stands for:

Random Access Memory

RAM is generally volatile memory.

It loses stored information when the power supply is removed.

The major types are:

A. SRAM

SRAM stands for:

Static Random Access Memory

It stores information using bistable latch/flip-flop type circuits.

Features:

High speed
No periodic refresh required
More expensive
Larger cell size
Used in cache memory

B. DRAM

DRAM stands for:

Dynamic Random Access Memory

It stores information using a capacitor-based storage cell.

Features:

High density
Lower cost per bit
Requires periodic refreshing
Slower than SRAM
Commonly used as main memory

2. ROM

ROM stands for:

Read Only Memory

ROM is non-volatile memory.

It retains its information even when power is removed.

Types include:

A. Mask ROM

The memory contents are programmed during manufacturing.

B. PROM

PROM stands for:

Programmable Read Only Memory

It can generally be programmed once by the user.

C. EPROM

EPROM stands for:

Erasable Programmable Read Only Memory

It can be erased using ultraviolet light and then reprogrammed.

D. EEPROM

EEPROM stands for:

Electrically Erasable Programmable Read Only Memory

It can be electrically erased and reprogrammed.

E. Flash Memory

Flash memory is a non-volatile semiconductor memory related to EEPROM technology and is commonly erased/programmed in blocks.

Memory Classification

Semiconductor Memory
        │
        ├──────── RAM
        │          │
        │          ├── SRAM
        │          └── DRAM
        │
        └──────── ROM
                   │
                   ├── Mask ROM
                   ├── PROM
                   ├── EPROM
                   ├── EEPROM
                   └── Flash

Q25(b). What is a Programmable Logic Device? Explain Its Types.

PLD stands for:

Programmable Logic Device

A PLD is a digital device whose internal logic structure can be programmed or configured by the user to implement required logic functions.

PLDs reduce the need for designing a large number of separate logic gates and interconnections.

Types of PLD

The important types include:

PROM
PLA
PAL
CPLD
FPGA

1. PROM

PROM stands for:

Programmable Read Only Memory

In the logic implementation view, it has:

Fixed AND array
Programmable OR array

It can be programmed by the user.

2. PLA

PLA stands for:

Programmable Logic Array

Both the AND and OR planes are programmable.

Inputs
   │
   ▼
Programmable
AND Plane
   │
   ▼
Programmable
OR Plane
   │
   ▼
Outputs

Advantage:

PLA provides high flexibility for implementing Boolean functions.

3. PAL

PAL stands for:

Programmable Array Logic

In a traditional PAL:

AND plane = Programmable
OR plane = Fixed

Inputs
   │
   ▼
Programmable
AND Plane
   │
   ▼
Fixed
OR Plane
   │
   ▼
Outputs

PAL is less flexible than PLA but can provide efficient implementation of logic functions.

4. CPLD

CPLD stands for:

Complex Programmable Logic Device

It consists of multiple programmable logic blocks connected through programmable interconnections.

Applications include:

Control circuits
Address decoding
Interface circuits
State machines
Digital control systems

5. FPGA

FPGA stands for:

Field Programmable Gate Array

An FPGA contains:

Configurable Logic Blocks
Programmable routing/interconnections
Input/Output blocks

It is used for implementing complex digital systems.

Basic FPGA Structure

┌──────┐   ┌──────┐   ┌──────┐
│ CLB  │───│ CLB  │───│ CLB  │
└──┬───┘   └──┬───┘   └──┬───┘
   │           │           │
   ├──── Programmable ─────┤
   │      Interconnect     │
   │           │           │
┌──┴───┐   ┌───┴──┐    ┌───┴──┐
│ CLB  │───│ CLB  │────│ CLB  │
└──────┘   └──────┘    └──────┘

PLD Comparison

Device	AND Plane	OR Plane	Main Feature
PROM	Fixed	Programmable	Memory-based logic
PLA	Programmable	Programmable	Highly flexible
PAL	Programmable	Fixed	Simple and efficient
CPLD	Programmable blocks	Programmable interconnect	Medium complexity
FPGA	Configurable logic	Configurable routing	Very high flexibility

FINAL PART-A ANSWER KEY

Question	Answer
Q1	D
Q2	A
Q3	D
Q4	A
Q5	D
Q6	B
Q7	C
Q8	A
Q9	C
Q10	B
Q11	JQ’ + K’Q
Q12	4 flip-flops
Q13	A
Q14	A
Q15	A
Q16	B
Q17	C
Q18	C
Q19	C
Q20	C

Most Important Topics for Exam

SR, JK, D and T Flip-Flops
Characteristic Tables and Equations
Master-Slave Flip-Flop
Counters and MOD Counters
K-map Minimization
Multiplexer Applications
Half Adder and Full Adder
Half Subtractor and Full Subtractor
2-bit Comparator
Moore and Mealy Sequence Detectors
RAM and ROM
SRAM and DRAM
PROM, PLA and PAL
CPLD and FPGA